GENERAL INFORMATION
SPECIFICATION OF THE AMU-LIA

General
Digital Quad(1)-Phase Lock-In Amplifier
Dynamic Reserve > 135 dB (1)
Noise < 6 nVrms/Hz0.5 @100kHz (1)
Time Constants 0.1 ms ... 1 ks (1)
Sensitivity 10 nV ... 10 V
Phase Resolution 0.001°

SIGNAL INPUT
Voltage Input single-ended SMB
Input coupling: dc or ac (f3dB = 2 Hz)
Input Impedance 100 kW || 20 pF (1) / 1 MW on requ.
Damage Threshold +/- 12 V
Bandwidth dc to 1 MHz (f3dB > 1 MHz)
Input Ranges ± 5 V, ± 500 mV, ± 50 mV (1)
Input Sensitivity 10 nV to 10 V
Typical Input Noise: Uac = 0 V, 50 W @ input
@ 100 kHz, high dynamic < 300 nVrms/Hz0.5
@ 100 kHz, normal dynamic < 50 nVrms/Hz0.5
@ 100 kHz, low dynamic < 8 nVrms/Hz0.5
RollOff 6 dB/oct, 12 dB/oct, 24 dB/oct
Time Constants 0,2 ms ... 5 s
Gain deviations between dynamic ranges: < 5%

REFERENCE OUTPUT
Internal Oscillator 10 mHz .. > 1 MHz
Frequency Resolution < 10 mHz
Frequency Accuracy +/- 50 ppm from 0 °C to 70 °C
Reference Output Voltage < 1 mVpp ... 15 Vpp
Output Noise Uac = 1 mV
@ 100 kHz < 200 nVrms/Hz0.5
PLL
Frequency range 1 Hz .. 1 MHz
Locking time < (100 ms+ 10 Cycle)
Phase error < 4 deg @ f < 1 kHz
Input amplitude TTL